In recent years complimentary metal-oxide-semiconductor (CMOS) devices have been used in very large scale integration (VLSI) circuits because of their high density and low power dissipation. However, when compared to bipolar devices, CMOS devices are considered to have low output drive capabilities and slow operating speeds. In order to overcome these disadvantages, bipolar metal-oxide-semiconductor (BIMOS) devices or bipolar complimentary metal-oxide-semiconductor (BICMOS) have been developed to increase both the speed and the output drive capabilities of the CMOS circuit. BICMOS devices generally include a CMOS integrated circuit with the drain regions of both the PMOS and NMOS transistors electrically connected to the base region of the bipolar transistor.
Several methods have been developed to fabricate both bipolar and MOS transistors in a single semiconductor substrate. One such method is described by H. Gahle in U.S. Pat. No. 4,475,279, entitled "Method of Making A Monolithic Integrated Circuit Comprising At Least One Pair of Complementary Field-Effect Transistors And At Least One Bipolar Transistor," issued Oct. 9, 1984. During the fabrication process for the CMOS devices, an additional masking and implantation step is carried out to form the base region of the bipolar transistor. The remaining components of the bipolar transistor are formed during the process steps used to form both the NMOS and PMOS transistors. Both the emitter region and the collector contact region are formed by diffusing impurities from the overlying emitter and collector electrodes, respectively. This process has the disadvantage of not being able to control the depth of the emitter region and the collector contact region because a diffusion technique is used to form these regions.
A method for fabricating bipolar and complimentary metal-oxide-semiconductor devices is also disclosed by V. Liang et al. in U.S. Pat. No. 4,346,512, entitled "Integrated Circuit Manufacturing Method," issued Aug. 31, 1982. In this process the base region for the NPN transistor is formed during the source and drain implantation step for the PMOS transistor. However, this method does not provide for a base contact region. Additionally, the source and drain regions are not self-aligned relative to the gate electrodes. Therefore, it is difficult to achieve high device densities utilizing this process.
There is a need for a method of fabricating VSLI circuits containing bipolar transistors and metal-oxide-semiconductor field-effect transistors having channel lengths in the submicron range. The MOS transistors produced by this method should have pocket regions, such as those described by S. Ogura et al. in the article entitled "A Half Micron MOSFET Using Double Implanted LDD," International Electron Device Meeting Technical Digest, 1982, pp. 718-721, so as to reduce the short channel effect associated with submicron channel length devices. The use of pocket regions to reduce the short channel effect is also described in U.S. Pat. No. 4,597,824, entitled "Method of Producing Semiconductor Device," issued July 1, 1986, to K. Shinada et al. Also, it would be desireable to fabricate a BICMOS integrated circuit using standard CMOS processing steps so that no additional ion implantation steps would be required to simultaneously form the bipolar transistor.